00001 00002 /***************************************************************************** 00003 00004 The following code is derived, directly or indirectly, from the SystemC 00005 source code Copyright (c) 1996-2006 by all Contributors. 00006 All Rights reserved. 00007 00008 The contents of this file are subject to the restrictions and limitations 00009 set forth in the SystemC Open Source License Version 2.4 (the "License"); 00010 You may not use this file except in compliance with such restrictions and 00011 limitations. You may obtain instructions on how to receive a copy of the 00012 License at http://www.systemc.org/. Software distributed by Contributors 00013 under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF 00014 ANY KIND, either express or implied. See the License for the specific 00015 language governing rights and limitations under the License. 00016 00017 *****************************************************************************/ 00018 00019 /***************************************************************************** 00020 00021 sc_export.cpp -- 00022 00023 Original Author: Bishnupriya Bhattachary, Cadence, Design Systems, 00024 25 August, 2003 00025 00026 *****************************************************************************/ 00027 00028 /***************************************************************************** 00029 00030 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 00031 changes you are making here. 00032 00033 Name, Affiliation, Date: 00034 Description of Modification: 00035 00036 *****************************************************************************/ 00037 00038 // $Log: sc_export.cpp,v $ 00039 // Revision 1.1.1.1 2006/12/15 20:31:35 acg 00040 // SystemC 2.2 00041 // 00042 // Revision 1.4 2006/01/26 21:00:50 acg 00043 // Andy Goodrich: conversion to use sc_event::notify(SC_ZERO_TIME) instead of 00044 // sc_event::notify_delayed() 00045 // 00046 // Revision 1.3 2006/01/13 18:47:42 acg 00047 // Added $Log command so that CVS comments are reproduced in the source. 00048 // 00049 00050 #include "sysc/communication/sc_export.h" 00051 #include "sysc/kernel/sc_simcontext.h" 00052 00053 namespace sc_core { 00054 00055 // ---------------------------------------------------------------------------- 00056 // CLASS : sc_export_base 00057 // 00058 // ---------------------------------------------------------------------------- 00059 00060 sc_export_base::sc_export_base() : sc_object(sc_gen_unique_name("export")) 00061 { 00062 simcontext()->get_export_registry()->insert(this); 00063 } 00064 00065 sc_export_base::sc_export_base(const char* name_) : sc_object(name_) 00066 { 00067 simcontext()->get_export_registry()->insert(this); 00068 } 00069 00070 sc_export_base::~sc_export_base() 00071 { 00072 simcontext()->get_export_registry()->remove(this); 00073 } 00074 00075 // called when construction is done 00076 00077 void 00078 sc_export_base::before_end_of_elaboration() 00079 { 00080 } 00081 00082 // called when elaboration is done (does nothing) 00083 00084 void 00085 sc_export_base::end_of_elaboration() 00086 {} 00087 00088 // called before simulation starts (does nothing) 00089 00090 void 00091 sc_export_base::start_of_simulation() 00092 {} 00093 00094 // called after simulation ends (does nothing) 00095 00096 void 00097 sc_export_base::end_of_simulation() 00098 {} 00099 00100 00101 // ---------------------------------------------------------------------------- 00102 // CLASS : sc_export_registry 00103 // 00104 // Registry for all exports. 00105 // FOR INTERNAL USE ONLY! 00106 // ---------------------------------------------------------------------------- 00107 00108 void 00109 sc_export_registry::insert( sc_export_base* export_ ) 00110 { 00111 if( sc_is_running() ) { 00112 SC_REPORT_ERROR(SC_ID_SC_EXPORT_AFTER_START_, export_->name()); 00113 } 00114 00115 #ifdef DEBUG_SYSTEMC 00116 // check if port_ is already inserted 00117 for( int i = size() - 1; i >= 0; -- i ) { 00118 if( export_ == m_export_vec[i] ) { 00119 SC_REPORT_ERROR(SC_ID_SC_EXPORT_ALREADY_REGISTERED_, export_->name()); 00120 } 00121 } 00122 #endif 00123 00124 /* 00125 //TBD: maybe we want to do this stuf for later 00126 00127 // append the port to the current module's vector of ports 00128 sc_module* curr_module = m_simc->hierarchy_curr(); 00129 if( curr_module == 0 ) { 00130 port_->report_error( SC_ID_PORT_OUTSIDE_MODULE_ ); 00131 } 00132 curr_module->append_port( port_ ); 00133 */ 00134 00135 // insert 00136 m_export_vec.push_back( export_ ); 00137 } 00138 00139 void 00140 sc_export_registry::remove( sc_export_base* export_ ) 00141 { 00142 if (size()==0) return; 00143 int i; 00144 for( i = size() - 1; i >= 0; -- i ) { 00145 if( export_ == m_export_vec[i] ) { 00146 break; 00147 } 00148 } 00149 if( i == -1 ) { 00150 SC_REPORT_ERROR(SC_ID_SC_EXPORT_NOT_REGISTERED_, export_->name()); 00151 } 00152 00153 // remove 00154 m_export_vec[i] = m_export_vec[size() - 1]; 00155 m_export_vec.resize(size()-1); 00156 } 00157 00158 // constructor 00159 00160 sc_export_registry::sc_export_registry( sc_simcontext& simc_ ) 00161 : m_simc( &simc_ ) 00162 { 00163 } 00164 00165 00166 // destructor 00167 00168 sc_export_registry::~sc_export_registry() 00169 { 00170 } 00171 00172 // called when construction is done 00173 00174 void 00175 sc_export_registry::construction_done() 00176 { 00177 for( int i = size() - 1; i >= 0; -- i ) { 00178 sc_export_base* e = m_export_vec[i]; 00179 if (e->get_interface() == 0) { 00180 SC_REPORT_ERROR(SC_ID_SC_EXPORT_NOT_BOUND_AFTER_CONSTRUCTION_, 00181 e->name()); 00182 } 00183 e->before_end_of_elaboration(); 00184 } 00185 } 00186 00187 // called when elaboration is done 00188 00189 void 00190 sc_export_registry::elaboration_done() 00191 { 00192 for( int i = size() - 1; i >= 0; -- i ) { 00193 m_export_vec[i]->end_of_elaboration(); 00194 } 00195 } 00196 00197 // called before simulation begins 00198 00199 void 00200 sc_export_registry::start_simulation() 00201 { 00202 for( int i = size() - 1; i >= 0; -- i ) { 00203 m_export_vec[i]->start_of_simulation(); 00204 } 00205 } 00206 00207 void 00208 sc_export_registry::simulation_done() 00209 { 00210 for( int i = size() - 1; i >= 0; -- i ) { 00211 m_export_vec[i]->end_of_simulation(); 00212 } 00213 } 00214 00215 } // namespace sc_core 00216 00217 // Taf!