00001 /***************************************************************************** 00002 00003 The following code is derived, directly or indirectly, from the SystemC 00004 source code Copyright (c) 1996-2008 by all Contributors. 00005 All Rights reserved. 00006 00007 The contents of this file are subject to the restrictions and limitations 00008 set forth in the SystemC Open Source License Version 3.0 (the "License"); 00009 You may not use this file except in compliance with such restrictions and 00010 limitations. You may obtain instructions on how to receive a copy of the 00011 License at http://www.systemc.org/. Software distributed by Contributors 00012 under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF 00013 ANY KIND, either express or implied. See the License for the specific 00014 language governing rights and limitations under the License. 00015 00016 *****************************************************************************/ 00017 00018 #ifndef __TLM_DMI_H__ 00019 #define __TLM_DMI_H__ 00020 00021 #include <systemc> 00022 00023 namespace tlm { 00024 00025 class tlm_dmi 00026 { 00027 public: 00028 00029 // Enum for indicating the access granted to the initiator. 00030 // The initiator uses gp.m_command to indicate it intention (read/write) 00031 // The target is allowed to promote DMI_ACCESS_READ or DMI_ACCESS_WRITE 00032 // requests to dmi_access_read_write. 00033 00034 enum dmi_access_e 00035 { DMI_ACCESS_NONE = 0x00 // no access 00036 , DMI_ACCESS_READ = 0x01 // read access 00037 , DMI_ACCESS_WRITE = 0x02 // write access 00038 , DMI_ACCESS_READ_WRITE = DMI_ACCESS_READ | DMI_ACCESS_WRITE // read/write access 00039 }; 00040 00041 tlm_dmi (void) 00042 { 00043 init(); 00044 } 00045 00046 void init (void) 00047 { 00048 m_dmi_ptr = 0x0; 00049 m_dmi_start_address = 0x0; 00050 m_dmi_end_address = (sc_dt::uint64)(-1); 00051 m_dmi_access = DMI_ACCESS_NONE; 00052 m_dmi_read_latency = sc_core::SC_ZERO_TIME; 00053 m_dmi_write_latency = sc_core::SC_ZERO_TIME; 00054 } 00055 00056 unsigned char* get_dmi_ptr (void) const {return m_dmi_ptr;} 00057 sc_dt::uint64 get_start_address (void) const {return m_dmi_start_address;} 00058 sc_dt::uint64 get_end_address (void) const {return m_dmi_end_address;} 00059 sc_core::sc_time get_read_latency (void) const {return m_dmi_read_latency;} 00060 sc_core::sc_time get_write_latency (void) const {return m_dmi_write_latency;} 00061 dmi_access_e get_granted_access (void) const {return m_dmi_access;} 00062 bool is_none_allowed (void) const {return m_dmi_access == DMI_ACCESS_NONE;} 00063 bool is_read_allowed (void) const {return (m_dmi_access & DMI_ACCESS_READ) == DMI_ACCESS_READ;} 00064 bool is_write_allowed (void) const {return (m_dmi_access & DMI_ACCESS_WRITE) == DMI_ACCESS_WRITE;} 00065 bool is_read_write_allowed (void) const {return (m_dmi_access & DMI_ACCESS_READ_WRITE) == DMI_ACCESS_READ_WRITE;} 00066 00067 void set_dmi_ptr (unsigned char* p) {m_dmi_ptr = p;} 00068 void set_start_address (sc_dt::uint64 addr) {m_dmi_start_address = addr;} 00069 void set_end_address (sc_dt::uint64 addr) {m_dmi_end_address = addr;} 00070 void set_read_latency (sc_core::sc_time t) {m_dmi_read_latency = t;} 00071 void set_write_latency (sc_core::sc_time t) {m_dmi_write_latency = t;} 00072 void set_granted_access (dmi_access_e a) {m_dmi_access = a;} 00073 void allow_none (void) {m_dmi_access = DMI_ACCESS_NONE;} 00074 void allow_read (void) {m_dmi_access = DMI_ACCESS_READ;} 00075 void allow_write (void) {m_dmi_access = DMI_ACCESS_WRITE;} 00076 void allow_read_write (void) {m_dmi_access = DMI_ACCESS_READ_WRITE;} 00077 00078 private: 00079 00080 // If the forward call is successful, the target returns the dmi_ptr, 00081 // which must point to the data element corresponding to the 00082 // dmi_start_address. The data is organized as a byte array with the 00083 // endianness of the target (endianness member of the tlm_dmi struct). 00084 00085 unsigned char* m_dmi_ptr; 00086 00087 // The absolute start and end addresses of the DMI region. If the decoder 00088 // logic in the interconnect changes the address field e.g. by masking, the 00089 // interconnect is responsible to transform the relative address back to an 00090 // absolute address again. 00091 00092 sc_dt::uint64 m_dmi_start_address; 00093 sc_dt::uint64 m_dmi_end_address; 00094 00095 // Granted access 00096 00097 dmi_access_e m_dmi_access; 00098 00099 // These members define the latency of read/write transactions. The 00100 // initiator must initialize these members to zero before requesting a 00101 // dmi pointer, because both the interconnect as well as the target can 00102 // add to the total transaction latency. 00103 // Depending on the 'type' attribute only one, or both of these attributes 00104 // will be valid. 00105 00106 sc_core::sc_time m_dmi_read_latency; 00107 sc_core::sc_time m_dmi_write_latency; 00108 }; 00109 00110 } // namespace tlm 00111 00112 #endif /* TLM_DMI_HEADER */
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